Add pre-built Vivado design, petalinux bsp and documentation updates

416e8b52 · Moss, Jason · 8df2c53c · 416e8b52 · 416e8b52 · 416e8b52
Commit 416e8b52 authored Feb 20, 2020 by Moss, Jason
--- a/.gitignore
+++ b/.gitignore
+# Ignore the following UltraZED-EV v2019.2 VCU TRD components
+
+# Ignore temporary files
+*~
+*.log
+*.jou
+
+# Ignore pl build folder
+pl/build
\ No newline at end of file
--- a/apu/vcu_petalinux_bsp/Release_Notes_v2019.2-vcu-uz7ev-cc.md
+++ b/apu/vcu_petalinux_bsp/Release_Notes_v2019.2-vcu-uz7ev-cc.md
--- a/apu/vcu_petalinux_bsp/uz7evcc_petalinux_v2019.2-vcu-only.bsp
+++ b/apu/vcu_petalinux_bsp/uz7evcc_petalinux_v2019.2-vcu-only.bsp
--- a/pl/constrs/uz7evcc_vcu.xdc
+++ b/pl/constrs/uz7evcc_vcu.xdc
@@ -8,4 +8,4 @@
 ## Pins
 #####
 set_property PACKAGE_PIN AC8 [get_ports {sysclk_uz7ev_clk_p}]
-set_property IOSTANDARD LVDS [get_ports {sysclk_uz7ev_clk_p}]
+set_property IOSTANDARD LVDS [get_ports {sysclk_uz7ev_clk_p}]
\ No newline at end of file
--- a/pl/designs/uz7evcc_vcu/bd.tcl
+++ b/pl/designs/uz7evcc_vcu/bd.tcl
--- a/pl/designs/uz7evcc_vcu/project.tcl
+++ b/pl/designs/uz7evcc_vcu/project.tcl
@@ -47,3 +47,4 @@ regenerate_bd_layout

 import_files
 save_bd_design
+
--- a/pl/prebuild/uz7evcc_vcu/uz7evcc_vcu.xsa
+++ b/pl/prebuild/uz7evcc_vcu/uz7evcc_vcu.xsa