Commit 8df2c53c authored by Moss, Jason's avatar Moss, Jason
Browse files

First working draft of v2019.2 VCU only port for uz7evcc

parent 7672c44e
#####
## Constraints for UZ7EV with VCU
## Version 1.0
#####
#####
## Pins
#####
set_property PACKAGE_PIN AC8 [get_ports {sysclk_uz7ev_clk_p}]
set_property IOSTANDARD LVDS [get_ports {sysclk_uz7ev_clk_p}]
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# global variables
set ::platform "uz7evcc"
set ::silicon "i"
# local variables
set design_nm "${::platform}_vcu"
set project_dir "build/$design_nm"
set ip_dir "srcs/ip"
set constrs_dir "constrs"
set scripts_dir "designs/$design_nm"
# set variable names
set part "xczu7ev-fbvb900-1-${::silicon}"
puts "INFO: Target part selected: '$part'"
# set up project
create_project $design_nm $project_dir -part $part -force
set board_lat [ get_board_parts -latest_file_version {*ultrazed_7ev_cc*} ]
set_property board_part $board_lat [current_project]
# set up IP repo
set_property ip_repo_paths $ip_dir [current_fileset]
update_ip_catalog -rebuild
# set up bd design
create_bd_design bd
source $scripts_dir/bd.tcl
# add hdl sources to project
make_wrapper -files [get_files ./$project_dir/$design_nm.srcs/sources_1/bd/bd/bd.bd] -top
# Use the pre-built wrapper file instead of the generated wrapper (uncomment the following 2 lines)
add_files -norecurse ./srcs/hdl/${design_nm}_wrapper.v
set_property top ${design_nm}_wrapper [current_fileset]
# Alternatively, use the generated wrapper (uncomment the following 2 lines)
#add_files -norecurse ./$project_dir/$design_nm.srcs/sources_1/bd/bd/hdl/bd_wrapper.v
#set_property top bd_wrapper [current_fileset]
add_files -fileset constrs_1 -norecurse $constrs_dir/${design_nm}.xdc
update_compile_order -fileset sources_1
set_property strategy Performance_NetDelay_low [get_runs impl_1]
validate_bd_design
update_compile_order -fileset sources_1
regenerate_bd_layout
import_files
save_bd_design
//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.2 (lin64) Build 2700185 Thu Oct 24 18:45:48 MDT 2019
//Date : Wed Dec 4 03:09:06 2019
//Host : xilinx_vivado_licensed_v2019.2 running 64-bit Ubuntu 18.04.1 LTS
//Command : generate_target uz7evcc_vcu_wrapper.bd
//Design : uz7evcc_vcu_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module uz7evcc_vcu_wrapper
(dip_switches_8bits_tri_i,
led_8bits_tri_o,
push_buttons_3bits_tri_i,
sysclk_uz7ev_clk_n,
sysclk_uz7ev_clk_p);
input [7:0]dip_switches_8bits_tri_i;
output [7:0]led_8bits_tri_o;
input [2:0]push_buttons_3bits_tri_i;
input sysclk_uz7ev_clk_n;
input sysclk_uz7ev_clk_p;
wire [7:0]dip_switches_8bits_tri_i;
wire [7:0]led_8bits_tri_o;
wire [2:0]push_buttons_3bits_tri_i;
wire sysclk_uz7ev_clk_n;
wire sysclk_uz7ev_clk_p;
bd bd_i
(.dip_switches_8bits_tri_i(dip_switches_8bits_tri_i),
.led_8bits_tri_o(led_8bits_tri_o),
.push_buttons_3bits_tri_i(push_buttons_3bits_tri_i),
.sysclk_uz7ev_clk_n(sysclk_uz7ev_clk_n),
.sysclk_uz7ev_clk_p(sysclk_uz7ev_clk_p));
endmodule
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