Add prebuilt design wrappers

pl/srcs/.gitignore

+# Ignore all files
+*
+
+# Include the gitignore
+!.gitignore
+
+# Allow subfolders
+!*/
+
+# Allow the following files and folders
+!uz7ev_evcc/**

pl/srcs/uz7ev_evcc/hdl/uz7ev_evcc_vcu_wrapper.v

+//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
+//Date        : Thu Sep  3 14:24:09 2020
+//Host        : xilinx_vivado_v2020.1 running 64-bit Ubuntu 18.04.2 LTS
+//Command     : generate_target bd_wrapper.bd
+//Design      : bd_wrapper
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module uz7ev_evcc_vcu_wrapper
+   (dip_switches_8bits_tri_i,
+    led_8bits_tri_o,
+    push_buttons_3bits_tri_i,
+    sysclk_uz7ev_clk_n,
+    sysclk_uz7ev_clk_p);
+  input [7:0]dip_switches_8bits_tri_i;
+  output [7:0]led_8bits_tri_o;
+  input [2:0]push_buttons_3bits_tri_i;
+  input sysclk_uz7ev_clk_n;
+  input sysclk_uz7ev_clk_p;
+
+  wire [7:0]dip_switches_8bits_tri_i;
+  wire [7:0]led_8bits_tri_o;
+  wire [2:0]push_buttons_3bits_tri_i;
+  wire sysclk_uz7ev_clk_n;
+  wire sysclk_uz7ev_clk_p;
+
+  bd bd_i
+       (.dip_switches_8bits_tri_i(dip_switches_8bits_tri_i),
+        .led_8bits_tri_o(led_8bits_tri_o),
+        .push_buttons_3bits_tri_i(push_buttons_3bits_tri_i),
+        .sysclk_uz7ev_clk_n(sysclk_uz7ev_clk_n),
+        .sysclk_uz7ev_clk_p(sysclk_uz7ev_clk_p));
+endmodule

pl/srcs/uz7ev_evcc/hdl/uz7ev_evcc_wrapper.v

+//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
+//Date        : Wed Sep  2 19:50:10 2020
+//Host        : xilinx_vivado_v2020.1 running 64-bit Ubuntu 18.04.2 LTS
+//Command     : generate_target bd_wrapper.bd
+//Design      : bd_wrapper
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module uz7ev_evcc_wrapper
+   (dip_switches_8bits_tri_i,
+    led_8bits_tri_o,
+    push_buttons_3bits_tri_i);
+  input [7:0]dip_switches_8bits_tri_i;
+  output [7:0]led_8bits_tri_o;
+  input [2:0]push_buttons_3bits_tri_i;
+
+  wire [7:0]dip_switches_8bits_tri_i;
+  wire [7:0]led_8bits_tri_o;
+  wire [2:0]push_buttons_3bits_tri_i;
+
+  bd bd_i
+       (.dip_switches_8bits_tri_i(dip_switches_8bits_tri_i),
+        .led_8bits_tri_o(led_8bits_tri_o),
+        .push_buttons_3bits_tri_i(push_buttons_3bits_tri_i));
+endmodule