Explore projects
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Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit
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Nguyen, Harry / aibox-facerec
Apache License 2.0Modification of XLX aibox-reid app into face recognition
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Machine learning example for the ZCU104 with FMC Quad-Camera module from Avnet
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Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit
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An example project that demonstrates how to create face detection and person detection GStreamer plugins using the Xilinx Vitis-AI-Library.
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The example design can be used as a reference of how to properly instantiate the Video TPG in a block design and configure a Linux build to generate (and display) test patterns using GStreamer. Four test pattern generator configurations are provided:
(1) Free Running mode (2) Free Running mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP (3) Rate Controlled mode (4) Rate Controlled mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP
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Simple project to allow developing accelerated applications on Ultra96v2 using Vitis Acceleration and PetaLinux.
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This lab descripts the process of running OpenAMP on the Zynq and Zynq Ultrascale+ MPSoC utilizing APUs and RPUs.
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This lab will focus on applying device tree modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.
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Developed with Vivado 2022.1, these behavioral simulations show how to use the Video Test Pattern Generator and highlight how to control the test pattern generation framerate using a Video Timing Controller and Video In to AXI Stream conversion IP. The simulation simulations a QQVGA (160x120) resolution frame size, showing 4 frames generated as fast as the TPG can generate them at 25MHz bus clock, then shows 4 frames generated with 60fps refresh rate timine (1.944MHz Pixel Clock).
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This lab describes the process for customizing the Xilinx Yocto Manifest to pull the users image modifications from their personal repo.
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UltraZED-EV Port of the ZCU106 VCU TRD
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