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Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit

Example showing how to build the platform and demo for the zcu104_vcu_ml reference design/demo

Scripted build examples for generating custom ZCU106 Vitis Platforms with Overlay Support, including DPU, SOFTMAX, VVAS HLS Accelerators, etc...)

This lab will provide the process to encrypt and authenticate the Xilinx Zynqmp boot images.

Overview of the Xilinx U-boot Implementation

The example design can be used as a reference of how to properly instantiate the Video TPG in a block design and configure a Linux build to generate (and display) test patterns using GStreamer. Four test pattern generator configurations are provided:

(1) Free Running mode (2) Free Running mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP (3) Rate Controlled mode (4) Rate Controlled mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP

A demo on Cypress PSoC 6 WiFi-BT Pioneer Kit for Avnet IoTConnect mbed C/C++ SDK - http://iotconnect.io/

Avnet IoTConnect Client mbed C/C++ SDK

Simple project to allow developing accelerated applications on Ultra96v2 using Vitis Acceleration and PetaLinux.

Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit

This article is a complete flow to create a Linux image using Yocto 2021.1.

Avnet IoTConnect Demo on STM32 Boards ST - B-L475E-IOT01A (DISCO_L475VG_IOT01A) / B-L4S5I-IOT01A