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UltraZED-EV Port of the ZCU106 VCU TRD

This lab descripts the process of running OpenAMP on the Zynq and Zynq Ultrascale+ MPSoC utilizing APUs and RPUs.

Example showing how to build the platform and demo for the zcu104_vcu_ml reference design/demo

A demo on Cypress PSoC 6 WiFi-BT Pioneer Kit for Avnet IoTConnect mbed C/C++ SDK - http://iotconnect.io/

The example design can be used as a reference of how to properly instantiate the Video TPG in a block design and configure a Linux build to generate (and display) test patterns using GStreamer. Four test pattern generator configurations are provided:

(1) Free Running mode (2) Free Running mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP (3) Rate Controlled mode (4) Rate Controlled mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP

Simple project to allow developing accelerated applications on Ultra96v2 using Vitis Acceleration and PetaLinux.

Scripted build examples for generating custom ZCU106 Vitis Platforms with Overlay Support, including DPU, SOFTMAX, VVAS HLS Accelerators, etc...)

This lab demos the process of adding applications to a Xilinx Yocto Image.

Test mkdocs runner

This lab will focus on applying U-Boot modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.

This lab will focus on applying device tree modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.

Avnet IoTConnect Demo on STM32 Boards ST - B-L475E-IOT01A (DISCO_L475VG_IOT01A) / B-L4S5I-IOT01A

Yocto meta-layer for MaaXBoard/Mini/Nano