Explore projects
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Example showing how to build the platform and demo for the zcu104_vcu_ml reference design/demo
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UltraZED-EV Port of the ZCU106 VCU TRD
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Example project showing how to package the Xilinx logiCORE FFT IP as an SDSoC C-Callable library.
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This lab will focus on applying Linux modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.
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The gitlab will demonstrate the process of creating a meta-user recipe to build custom R5 RPU applications.
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Learn how to get started working with the YoloV3 model with Darknet53 backbone from the Model Zoo in Vitis AI 3.5, including retraining the model with the COCO 2017 training dataset.
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Utilities / Binaries / Scripts / Config files to build a rootfs for different boards
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This lab will focus on applying U-Boot modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.
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