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This lab descripts the process of running OpenAMP on the Zynq and Zynq Ultrascale+ MPSoC utilizing APUs and RPUs.

Example showing how to build the platform and demo for the zcu104_vcu_ml reference design/demo

UltraZED-EV Port of the ZCU106 VCU TRD

Example project showing how to package the Xilinx logiCORE FFT IP as an SDSoC C-Callable library.

This lab will focus on applying Linux modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.

The gitlab will demonstrate the process of creating a meta-user recipe to build custom R5 RPU applications.

Avnet IoTConnect Client mbed C/C++ SDK

Yocto meta-layer for MaaXBoard/Mini/Nano

This lab describes the process for customizing the Xilinx Yocto Manifest to pull the users image modifications from their personal repo.

Docker is recommended for building iMX Embedded Linux

Utilities / Binaries / Scripts / Config files to build a rootfs for different boards

Developed with Vivado 2022.1, these behavioral simulations show how to recover native video timing from an AXI4 Video Stream and how to convert natively timed video to AXI4 Streams using catalog IP blocks including the Video Tiiming Controller, AXI4 Stream to Video Out and Video In to AXI4 Stream IP. AXI4 Stream input video is simulated using a Video Test Pattern Generator and the AXI4 Video Stream Remapper IP to show how to convert from 2 pixels per clock to 1 pixel per clock.

Learn how to get started working with the YoloV3 model with Darknet53 backbone from the Model Zoo in Vitis AI 3.5, including retraining the model with the COCO 2017 training dataset.

iMX BSPs (Board Support Packages)