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Developed with Vivado 2022.1, these behavioral simulations show how to recover native video timing from an AXI4 Video Stream and how to convert natively timed video to AXI4 Streams using catalog IP blocks including the Video Tiiming Controller, AXI4 Stream to Video Out and Video In to AXI4 Stream IP. AXI4 Stream input video is simulated using a Video Test Pattern Generator and the AXI4 Video Stream Remapper IP to show how to convert from 2 pixels per clock to 1 pixel per clock.

Simple project to allow developing accelerated applications on Ultra96v2 using Vitis Acceleration and PetaLinux.

Example showing how to build the platform and demo for the zcu104_vcu_ml reference design/demo

Developed with Vivado 2022.1, these behavioral simulations show how to use the Video Test Pattern Generator and highlight how to control the test pattern generation framerate using a Video Timing Controller and Video In to AXI Stream conversion IP. The simulation simulations a QQVGA (160x120) resolution frame size, showing 4 frames generated as fast as the TPG can generate them at 25MHz bus clock, then shows 4 frames generated with 60fps refresh rate timine (1.944MHz Pixel Clock).

This lab descripts the process of running OpenAMP on the Zynq and Zynq Ultrascale+ MPSoC utilizing APUs and RPUs.

Avnet IoTConnect Client mbed C/C++ SDK

This lab will focus on applying Linux modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.

Example project showing how to package the Xilinx logiCORE FFT IP as an SDSoC C-Callable library.

This lab demos the process of adding applications to a Xilinx Yocto Image.

Yocto meta-layer for MaaXBoard/Mini/Nano

This lab will focus on applying device tree modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.

This lab provides an example of the XSCT workflow for yocto 2024.2. Note - SDT is the recommend workflow not XSCT.

Utilities / Binaries / Scripts / Config files to build a rootfs for different boards

The example design can be used as a reference of how to properly instantiate the Video TPG in a block design and configure a Linux build to generate (and display) test patterns using GStreamer. Four test pattern generator configurations are provided:

(1) Free Running mode (2) Free Running mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP (3) Rate Controlled mode (4) Rate Controlled mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP