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Instructions for getting setup to use TVM with Zynq UltraScale+ devices.

This lab will focus on applying U-Boot modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.

Example design for generating live video input from the PL to the PS DisplayPort subsystem.

This lab descripts the process of running OpenAMP on the Zynq and Zynq Ultrascale+ MPSoC utilizing APUs and RPUs.

This lab will document the process for running an application on the secondary real-time r5 processor (RPU1) using split mode.

Overview of the Xilinx U-boot Implementation

This lab demos the process of adding applications to a Xilinx Yocto Image.

Configurable symmetric FIR filter example for the AMD Versal AIE

This GitLab repository demonstrates the process of creating an application SDK for cross-compiling applications. The compiled applications can then be copied onto an SD card root filesystem (rootFS) for testing.

Developed with Vivado 2022.1, these behavioral simulations show how to recover native video timing from an AXI4 Video Stream and how to convert natively timed video to AXI4 Streams using catalog IP blocks including the Video Tiiming Controller, AXI4 Stream to Video Out and Video In to AXI4 Stream IP. AXI4 Stream input video is simulated using a Video Test Pattern Generator and the AXI4 Video Stream Remapper IP to show how to convert from 2 pixels per clock to 1 pixel per clock.

Yocto meta-layer for MaaXBoard/Mini/Nano

The gitlab will demonstrate the process of creating a meta-user recipe to build custom R5 RPU applications.