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This GitLab repository demonstrates the process of creating an application SDK for cross-compiling applications. The compiled applications can then be copied onto an SD card root filesystem (rootFS) for testing.

Jason's collection of custom Vitis Platform recipes. NOTE: The platforms in this repository are for training, debug and integration. WARNING: Makefile stages have been broken up into shell scripts on the back end and MAKE dependencies have been removed. If a MAKE stage fails the build will continue, so be sure to check the console log for errors when using projects from this repository.

A demo on Cypress PSoC 6 WiFi-BT Pioneer Kit for Avnet IoTConnect mbed C/C++ SDK - http://iotconnect.io/

Simple project to allow developing accelerated applications on Ultra96v2 using Vitis Acceleration and PetaLinux.

Developed with Vivado 2022.1, these behavioral simulations show how to recover native video timing from an AXI4 Video Stream and how to convert natively timed video to AXI4 Streams using catalog IP blocks including the Video Tiiming Controller, AXI4 Stream to Video Out and Video In to AXI4 Stream IP. AXI4 Stream input video is simulated using a Video Test Pattern Generator and the AXI4 Video Stream Remapper IP to show how to convert from 2 pixels per clock to 1 pixel per clock.

Example showing how to build the platform and demo for the zcu104_vcu_ml reference design/demo

UltraZED-EV Port of the ZCU106 VCU TRD

This lab descripts the process of running OpenAMP on the Zynq and Zynq Ultrascale+ MPSoC utilizing APUs and RPUs.

Developed with Vivado 2022.1, these behavioral simulations show how to use the Video Test Pattern Generator and highlight how to control the test pattern generation framerate using a Video Timing Controller and Video In to AXI Stream conversion IP. The simulation simulations a QQVGA (160x120) resolution frame size, showing 4 frames generated as fast as the TPG can generate them at 25MHz bus clock, then shows 4 frames generated with 60fps refresh rate timine (1.944MHz Pixel Clock).

Example project showing how to package the Xilinx logiCORE FFT IP as an SDSoC C-Callable library.

This article is a complete SDT flow to create a Linux image using Yocto 2024.2.

ZCU104 DPU Example Designs for the Vivado Flow.

This lab will focus on applying U-Boot modifications to a 2024.2 Xilinx Yocto image created with the Xilinx Yocto Manifest.

UUU (Universal Update Utility)

Xilinx Petalinux GStreamer Command and Pipeline Element Reference.