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Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit

Modification of XLX aibox-reid app into face recognition

An example project that demonstrates how to create face detection and person detection GStreamer plugins using the Xilinx Vitis-AI-Library.

Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit

Machine learning example for the ZCU104 with FMC Quad-Camera module from Avnet

The example design can be used as a reference of how to properly instantiate the Video TPG in a block design and configure a Linux build to generate (and display) test patterns using GStreamer. Four test pattern generator configurations are provided:

(1) Free Running mode (2) Free Running mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP (3) Rate Controlled mode (4) Rate Controlled mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP

This lab will focus on applying device tree modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.

Simple project to allow developing accelerated applications on Ultra96v2 using Vitis Acceleration and PetaLinux.

Jason's collection of custom Vitis Platform recipes. NOTE: The platforms in this repository are for training, debug and integration. WARNING: Makefile stages have been broken up into shell scripts on the back end and MAKE dependencies have been removed. If a MAKE stage fails the build will continue, so be sure to check the console log for errors when using projects from this repository.

UltraZED-EV Port of the ZCU106 VCU TRD

This lab descripts the process of running OpenAMP on the Zynq and Zynq Ultrascale+ MPSoC utilizing APUs and RPUs.

iMX BSPs (Board Support Packages)

Example showing how to build the platform and demo for the zcu104_vcu_ml reference design/demo