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Modification of XLX aibox-reid app into face recognition

Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit

An example project that demonstrates how to create face detection and person detection GStreamer plugins using the Xilinx Vitis-AI-Library.

Machine learning example for the ZCU104 with FMC Quad-Camera module from Avnet

Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit

Ports of Xilinx TRD reference projects to the Avnet UltraZED UZ7EV SOM + IO Carrier Card

This lab descripts the process of running OpenAMP on the Zynq and Zynq Ultrascale+ MPSoC utilizing APUs and RPUs.

Developed with Vivado 2022.1, these behavioral simulations show how to recover native video timing from an AXI4 Video Stream and how to convert natively timed video to AXI4 Streams using catalog IP blocks including the Video Tiiming Controller, AXI4 Stream to Video Out and Video In to AXI4 Stream IP. AXI4 Stream input video is simulated using a Video Test Pattern Generator and the AXI4 Video Stream Remapper IP to show how to convert from 2 pixels per clock to 1 pixel per clock.

Yocto meta-layer for MaaXBoard/Mini/Nano

Developed with Vivado 2022.1, these behavioral simulations show how to use the Video Test Pattern Generator and highlight how to control the test pattern generation framerate using a Video Timing Controller and Video In to AXI Stream conversion IP. The simulation simulations a QQVGA (160x120) resolution frame size, showing 4 frames generated as fast as the TPG can generate them at 25MHz bus clock, then shows 4 frames generated with 60fps refresh rate timine (1.944MHz Pixel Clock).