Explore projects
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Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit
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Nguyen, Harry / aibox-facerec
Apache License 2.0Modification of XLX aibox-reid app into face recognition
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An example project that demonstrates how to create face detection and person detection GStreamer plugins using the Xilinx Vitis-AI-Library.
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Machine learning example for the ZCU104 with FMC Quad-Camera module from Avnet
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Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit
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The example design can be used as a reference of how to properly instantiate the Video TPG in a block design and configure a Linux build to generate (and display) test patterns using GStreamer. Four test pattern generator configurations are provided:
(1) Free Running mode (2) Free Running mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP (3) Rate Controlled mode (4) Rate Controlled mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP
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Jason's collection of custom Vitis Platform recipes. NOTE: The platforms in this repository are for training, debug and integration. WARNING: Makefile stages have been broken up into shell scripts on the back end and MAKE dependencies have been removed. If a MAKE stage fails the build will continue, so be sure to check the console log for errors when using projects from this repository.
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This lab demos the process of adding applications to a Xilinx Yocto Image.
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This lab will focus on applying device tree modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.
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Simple project to allow developing accelerated applications on Ultra96v2 using Vitis Acceleration and PetaLinux.
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Developed with Vivado 2022.1, these behavioral simulations show how to recover native video timing from an AXI4 Video Stream and how to convert natively timed video to AXI4 Streams using catalog IP blocks including the Video Tiiming Controller, AXI4 Stream to Video Out and Video In to AXI4 Stream IP. AXI4 Stream input video is simulated using a Video Test Pattern Generator and the AXI4 Video Stream Remapper IP to show how to convert from 2 pixels per clock to 1 pixel per clock.
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This lab descripts the process of running OpenAMP on the Zynq and Zynq Ultrascale+ MPSoC utilizing APUs and RPUs.
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UltraZED-EV Port of the ZCU106 VCU TRD
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