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An example project that demonstrates how to create face detection and person detection GStreamer plugins using the Xilinx Vitis-AI-Library.

Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit

Modification of XLX aibox-reid app into face recognition

Machine learning example for the ZCU104 with FMC Quad-Camera module from Avnet

Port of design modules from the ZCU106 v2019.2 VCU TRD to the UltraZED-EV Starter Kit

This lab will focus on applying device tree modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.

The example design can be used as a reference of how to properly instantiate the Video TPG in a block design and configure a Linux build to generate (and display) test patterns using GStreamer. Four test pattern generator configurations are provided:

(1) Free Running mode (2) Free Running mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP (3) Rate Controlled mode (4) Rate Controlled mode with Colorspace Conversion and Scaling using the Video Processing Subsystem IP

This lab will focus on applying U-Boot modifications to a 2021.1 Xilinx Yocto image created with the Xilinx Yocto Manifest.

Test mkdocs runner

This lab demos the process of adding applications to a Xilinx Yocto Image.

Simple project to allow developing accelerated applications on Ultra96v2 using Vitis Acceleration and PetaLinux.

A demo on Cypress PSoC 6 WiFi-BT Pioneer Kit for Avnet IoTConnect mbed C/C++ SDK - http://iotconnect.io/

Scripted build examples for generating custom ZCU106 Vitis Platforms with Overlay Support, including DPU, SOFTMAX, VVAS HLS Accelerators, etc...)

This lab descripts the process of running OpenAMP on the Zynq and Zynq Ultrascale+ MPSoC utilizing APUs and RPUs.